AL4CE205/215/225/235/245 256, 512, 1k, 2k, 4k x 18 advanced synchronous fifos applications - multimedia system - atm switches - routers - cable modems - wireless base stations - sonet(synchronous optical network) multiplexers - tb c(time base corrector) - hard disk cache memory description the al4ce2x5 series memory products are high - performance, low - power 18bit read/write fifo (first - in - first - out) memory chip designed to buffer high speed streaming data for a wide range of applications. the al4ce2x5 fifo memories are the advanced version of al4cs2x5. this product series support additional functions, such as bus - matching, endian select an d retransmit, can benefit designing efforts. ordering information part number AL4CE205, al4ce215, al4ce225, al4ce235, al4ce245 package 64 - pin plastic tqfp and stqfp power supply +3.3v 10% tqfp, stqfp package top view al4ce2 x 5 x - xx - xx xxxx xxxxx averlogic 64 17 32 33 16 1 48 49 features high performance, low - power, fifo(first - in first - out) memory 256 x 18 bit i/o port (AL4CE205) 512 x 18 bit i/o port (al4ce215) 1k x18 bit 1/o port (al4ce225) 2k x18 bit i/o port (al4ce23 5) 4k x18 bit i/o port (al4ce245) high clock speed ( 133mhz) fully independent read/write access retransmit the data (reread the data) empty, full, half full and programmable almost empty, almost full flags output enable control (data skipping) user select able input and output bus width big/little - endian word format selectable 3.3v 10% power supply with 5v signal tolerant input standard 64 - pin tqfp and stqfp
a ver l ogic t echnologies , i nc . tel : 1 408 361 - 0400 e - mail: sales@averlogic.com url: www.averlogic.com july 10, 2001 (256,512, 1k ,2k, 4k) x18 memory array input buffer output buffer write control logic read control logic flag logic control logic write pointer read pointer offset regissers reset logic input data bus output data bus /oe wclk /wen /ld /rs rclk /ren /ff /ef /hf /paf /pae /beb /rt /iw /ow figure 1. al4ce2x5 fifo block diagram t he 18bit input and output ports operate independently at a maximum speed of 133 mhz. the built - in address decoder and pointer managing circuits provide a straightforward bus interface to serially read/write memory that reduces inter - chip design efforts. t he al4ce2x5 embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags.. etc.) offer flexible memory management. these fifos support up to 18bit input and output dat a bus - width that is controlled by separate clock and enable signals respectively. the input data is acquired at each rising edge of a free running write clock while a write enable control pin is asserted. the output data is available after each rising ed ge of a free running read clock while a read enable and output enable control pins are asserted. when output enable (/oe) is low, the data output bus is active. if /oe is high, the output data bus will be in a high - impedance. this signal can control whe ther the data is going to be skipped during the read operation. the fifo full/empty, half - full and programmable almost full/almost empty flags are powerful functions that can help controlling software to manipulate the fifo more easily or to do retransmi t operation. bus - matching feature can flexibly configure input and output bus width. the chip can automatically convert the input data bus width to match up output data bus width by packing or unpacking the data. a big - endian/little - endian data word for mat is provided to invert the read - in bytes sequence for output. and the retransmit function allows data to be reread from the fifo more than once. these chips are available as a 64pin tqfp and stqfp package d istributed by :
|
